The performance of a digital system, such as a central processing unit (CPU), is often measured by its clock rate, which is the frequency at which the system is running and is used as an indicator of the processor's speed. It is measured in clock cycles per second or its equivalent, the hertz (Hz). With the advancement of technology, the speeds of digital systems continue to increase. CPUs designed for high-performance markets might require custom designs for each of these items to achieve frequency, power-dissipation, and chip-area goals. Control logic implementation techniques (logic synthesis using CAD tools) can be used to implement data paths, register files, and clocks. However, as the speed of modern digital systems further progresses well above gigahertz (GHz), it is becoming increasingly difficult to design and debug these high speed digital systems. It is also more difficult to understand the characteristics of the CPU that are limiting the circuit speed. For example, in certain implementations, as the system clock is increased, system speed degradation may be observed. In such instances, it is difficult to determine the portion of the circuit and program operation state responsible for the speed degradation.
It is therefore desirable to provide a system and method for determining events that limit system performance at high speed.